1. Field of the Invention
The present invention relates to a lateral bipolar transistor for an integrated circuit and a method of manufacturing the lateral bipolar transistor, and, more particularly, to a bipolar and complementary MOS transistor (BiCMOS) circuit using the lateral bipolar transistor and its method of manufacture.
2. Description of the Related Art
BiCMOS circuits including high speed analog circuitry are in high demand for computer and communication applications. A conventional BiCMOS circuit has both bipolar transistors and MOS transistors and in a single circuit on a common substrate. MOS transistors are typically used in digital circuits while bipolar transistors are typically used in analog circuits, and a BiCMOS circuit combines and integrates these transistors in a common monolithic semiconductor structure. Accordingly, in fabricating BiCMOS circuits, the formation of the MOS transistors and bipolar transistors must be compatible to be integrated into a common process scheme. Moreover, to control production cost, time and complexity, there remains a constant need in the BiCMOS process field for new design approaches that limit and reduce the overall number of process steps.
Lateral bipolar type transistors are used in BiCMOS devices as they provide good linearity and they generally are amenable to high volume production. The lateral bipolar transistors generally involve three distinct semiconductor regions of alternating conductivities, e.g., PNP or NPN, which extend along a common surface region of a substrate so as to form a lateral PNP (LPNP) or lateral NPN (LNPN), respectively. A need exists for a process sequence that would accomodate formation of a lateral bipolar transistor (e.g., LPNPs) for a BiCMOS circuit in the same area otherwise defined for a vertical bipolar device (viz., a vertical NPN device) without requiring additional process steps compared to those required to form vertical bipolar devices in the BiCMOS process. It also would be desirable to reduce the lateral spacing between emitters and collectors in LPNPs of BiCMOS devices. Narrower spacing between emitters and collectors in LPNPs is conducive to increasing gain and frequency response in the devices.
Additionally, for analog circuits in general using bipolar transistors, the magnitude of the current gain, maximum operating frequency, and Early voltage properties generally provide an indication of the high speed capabilities of the circuitry. Moreover, larger values of the product of the beta (xcex2) value (i.e., the current gain) of the transistor times the Early voltage also provides an indication of the high performance capabilities of the circuit. As known, a transistor""s beta (xcex2) value is the ratio of its output current (IC) to its input current (IB) determined while the transistor""s collector-to-emitter voltage (VCE) is held constant. The current gain of a transistor circuit corresponds identically to the transistor""s beta (xcex2) value for a common-emitter transistor circuit.
The Early effect phenomenon is also well known and it is based upon experimental observations that when the output characteristics curves, i.e., the plots of measured data of collector current versus collector voltage for different base current, of a bipolar transistor are extrapolated back to the point of zero collector current, that the curves all intersect at a common negative voltage. This voltage is the Early voltage, and it is typically represented as VA. High Early voltage is desired in analog circuits to prevent drastic swings from occuring in the collector current.
However, an impediment in the past to improving the high speed performance of an analog circuit with lateral bipolar transistors has been a tradeoff relationship that exists between the Early voltage, on one hand, and the current gain or the operational frequency on the other. Namely, improvements (increases) provided in either current gain or Early voltage in prior bipolar transistor designs have tended to be accompanied by an offsetting reduction in the other property such that the net overall performance of the circuit was not significantly improved. For example, the product of current gain (or beta) times the Early voltage, as a measure of performance capability, would remain essentially the same in value because if one property was increased the other property would seesaw down a cancelling amount. Therefore, a need also exists for lateral bipolar transistor architecture permitting enhancements to be made to either the Early voltage or the current gain (or operational frequency) without the improvements being effectively cancelled out due to an offsetting reduction occuring in the other transistor property. In that way, a meaningful net improvement in circuit performance might be provided at the design level.
In any event, the prior art fails to satisfactorily address and meet one or more of the above-mentioned needs and problems associated with conventional semiconductor devices using lateral bipolar transistors in general and conventional BiCMOS technology in particular.
For instance, U.S. Pat. No. 5,187,109 describes a process for making BiCMOS integrated circuits which include a bipolar transistor and MOS transistors. The emitter and collector are located in the same active region with a remote base contact made to a buried N region. The emitter is formed by diffusion from a layer of P+ polycrystalline silicon, and the P+ polycrystalline layer also serves as the gates of the MOS transistors. The base region is located directly under an insulator which is covered by the P+ polycrystalline layer used to form the emitter. A P+ S/D of the PMOS is the collector, and it is self-aligned to the base. An emitter field plate is used that is self-aligned to the collector to minimize E-C capacitance. The device is isolated with a buried N connection to cathode. A polycrystalline layer is used to contact deep buried N regions, and a CMOS spacer is used to prevent a short to the anode. However, U.S. Pat. No. 5,187,109 fails to teach a lateral bipolar transistor architecture in which the current gain or Early voltage can be enhanced without sacrificing the other property in a proportional manner.
Sun, et al., IEEE Transactrions on Electron Devices, vol. 39, no. Dec. 12, 1992, pp. 2733-2739, and commonly assigned U.S. Pat. No. 5,824,560, describe BiCMOS process technology providing a gated lateral PNP with metal silicide contacts arranged on the surface of polysilicon electrodes and on adjacent P+ surface regions provided in the substrate, where conventional lateral insulation portions or oxide spacers are formed on the sides of the polysilicon electrodes before subsequent metal silicide processing is performed, and the oxide spacers laterally intervene and laterally space the polysilicon electrodes from the P+ surface regions, and hence increases the spacing between adjacent polysilicon electrodes. Therefore, the gain and frequency response in the devices described in the Sun et al. publication and the U.S. Pat. No. 5,824,560 patent can be expected to be non-optimal. Additionally, as with the U.S. Pat. No. 5,197,109 patent, the Sun et al. publication and the U.S. Pat. No. 5,824,560 patent also fail to teach a lateral bipolar transistor architecture in which the current gain or Early voltage can be favorably improved without sacrificing the other property in a proportional manner.
Consequently, a need has existed in the art for a lateral bipolar transistor architecture that would support and enable high performance, high speed BiCMOS circuits technology, and a methodology for assimilating the formation of such bipolar transistor architecture into a BiCMOS process without necessitating additional process steps. The present invention fulfills the above and other needs.
According to the present invention, a lateral bipolar transistor is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit having both bipolar and CMOS devices, the lateral bipolar transistor being formed according to the BiCMOS method and without additional steps relative to formation of vertical bipolar devices if provided in the same area.
To accomplish these and other advantages and benefits, a lateral bipolar transistor made according to this invention generally has the following features. An active base region is formed over a substrate of an opposite conductivity type. The active base region preferably is formed on an intervening buried region of the same conductivity type provided on the substrate. The active base region advantageously is formed as an epitaxial layer of monocrystalline semiconductor material doped with impurities of appropriate conductivity for the active base of the lateral bipolar transistor. Collector regions having unique architecture for a lateral bipolar transistor application, along with an emitter region, are formed in this same active base region.
The collector of the lateral bipolar transistor is provided by forming moderately doped collector well regions of a conductivity type opposite to that of the active base region which laterally bound an intervening active base region to provide an LPNP. The collector well generally, but not necessarily, is formed having a depth extending approximately through the entire thickness of the active base region until reaching the buried region. An emitter is provided including an emitter well region formed in the surface of the active base region at a location laterally between and spaced from the collector well regions. The collector and emitter further include conductive layers of the same conductivity type arranged at the surface of the active base region over the respective collector and emitter well regions. The doped conductive layers, preferably doped polysilicon, serve as a contact layer for the collector and emitter upon which further electrical contact layers can be formed, such as metal silicides. Doped polysilicon type conductive layers advantageously can be used as a source of dopant that is diffused into the active base region to form the emitter well region at the location laterally between the collector well regions, as well as to form highly doped shallow surface well regions in the collector well regions to provide a low resistance contact with the polysilicon conductive layers.
Although the present invention is equally applicable to forming either LPNPs or NPNs, significant performance enhancements have been observed in particular,where the invention is applied to fabrication of LPNPs. That is to say, an integrated circuit of one embodiment of this invention implements the unique moderately doped collector well region structures as P well regions of a collector of an LPNP, and the resulting circuitries are endowed with significantly enhanced performance capabilities. In particular, the product of the current gain and Early voltage is significantly increased due to the presence of the P well regions. Another advantage accruing from the provision of the P well regions of the present invention is that they effectively narrow the spacing between the emitter and collector, i.e., the base width, which helps to increase gain and frequency response. Additionally, the laterally spacing between the doped polysilicon portions of the emitter and collector is defined in this invention by a silicide protect layer formed on the polysilicon portions, instead of conventional LOCOS regions or oxide spacers, which further reduces the lateral spacing, and therefore the base width. Beta values for the LPNPs of this invention are greater than approximately 100, and generally about 100-150 and even higher. In any event, the LPNPs incorporating the unique P well regions in the collectors display a significant increase in the product of the current gain and the Early voltage. The increase in the product of the Early voltage and the current gain has been observed to be a factor as high as about 6 times the value associated with a similar structure except lacking the P well structures provided in the collectors according to the present invention.
Through this inventive lateral bipolar transistor architecture, the present invention defies the conventional wisdom regarding the offsetting tradeoff relationship expected to occur between changes in current gain and Early voltage in bipolar transistor circuitry. For instance, this means that the increases in current gain achieved by the inventive lateral bipolar transistors are not effectively cancelled out by losses in Early voltage, because only a relatively small reduction actually results in the Early voltage despite the huge increases in current gain. Consequently, the high product value of the current gain and Early voltage achieved in the lateral bipolar transistors of this invention facilitates the building of linear circuits. Also, all of the current gain, Early voltage and frequency response can be provided at relatively high values in the inventive lateral bipolar transistors to provide high speed performance.
Another important discovery embodied by the present invention is the determination that the thickness of an epitaxial layer used as the active base region has a notable impact on the frequency response of the circuit. In identifying this relationship, it has been determined that better response is found to be a positive function of the thickness of the epitaxial layer. By fabricating lateral PNPs with the above-mentioned inventive design precepts in mind, lateral PNPs according to the invention have gain at frequency up to 1 GHz.
Importantly, the lateral bipolar transistors of the present invention can be formed in the course of a BiCMOS process in an active area otherwise defined for a conventional vertical PNP device without increasing the number of process steps required.